1. Field of the Invention
The present invention relates to integrated circuit capacitors in semiconductor integrated circuits (ICs), and more particularly, to integrated circuit capacitors in silicon-on-insulator (SOI) integrated circuits.
2. Description of the Related Art
In general, discrete capacitors typically include a dielectric material that separates two parallel plates. They are used to hold charge or to transmit an AC signal and block a DC signal. Capacitance is the amount of charge a capacitor can hold per volt and is measured in farads (F).
The textbook entitled xe2x80x9cSemiconductor Devices: Physics and Technologyxe2x80x9d, by S.M. Sze (John Wiley and Sons, 1985), provides a brief discussion of integrated circuit capacitors in Chapter 12. As stated therein, there are basically two types of capacitors that have been used in ICs: MOS capacitors and p-n junctions. A typical MOS (metal-oxide-semiconductor) capacitor, illustrated in FIGS. 1A and 1B, can be fabricated by using a heavily doped region 20 (such as an emitter region) as one plate, the top metal electrode 22 as the other plate, and the intervening oxide layer 24 as the dielectric. To form a MOS capacitor, a thick oxide layer 26 is thermally grown on a silicon substrate 28. Next, a window is lithographically defined and then etched in the oxide. Diffusion or ion implantation is used to form a p+ -region 20 in the window area, while the surrounding thick oxide 26 serves as a mask. A thin oxide layer 24 is then thermally grown in the window area, followed by a metallization step. The capacitance per unit area is given by:
C=xcex5ox/d F/cm2
where xcex5ox is the dielectric permittivity of silicon dioxide (the dielectric constant xcex5ox/xcex5O is 3.9) and d is the thin-oxide thickness. To increase the capacitance further, insulators with higher dielectric constants have been suggested, such as for example, Si3N4 and Ta2O5 with dielectric constants of 8 and 22, respectively. The MOS capacitance is essentially independent of the applied voltage, because the lower plate 20 of the capacitor is made of heavily doped material. This also reduces the series resistance associated with it.
The p-n junction is sometimes used as a capacitor in an integrated circuit. FIGS. 2A and 2B illustrates an n+xe2x88x92p junction capacitor, the structure of which forms part of a bipolar transistor. As a capacitor, the device is usually reverse-biased, i.e., the p-region 30 is reverse-biased with respect to the n+xe2x88x92region 32. The capacitance is not a constant but varies as (VR+Vbi)xe2x88x92xc2xd, where VR is the applied voltage and Vbi is the built-in potential. The series resistance is considerably higher than that of a MOS capacitor because the p-region 30 has higher resistivity than does the p+ -region.
One disadvantage of the MOS capacitor of FIGS. 1A and 1B is that it includes a significant parasitic (or junction) capacitance component due to the substrate material 28. Variations in the applied voltage may result in variations in this parasitic capacitance which may result in possible frequency modulation of the signal. Such frequency modulation can be detrimental in analog ICs, such as for example, ICs used in wireless communications applications. Specifically, wireless communications devices use high-frequency signals: 900 MHz to 1900 MHz for cellular phones and higher (up to 6 GHz) for other systems, such as wireless LANs. The proposed Bluetooth standard calls for operation in the unlicensed ISM band at 2.4 GHz. Signals at such frequencies, i.e., high radio frequencies (RF), are difficult to generate and control. They also have a tendency to interfere with each other, as they are easily coupled by parasitic properties present in all electronic components, including ICs. In ICs, many of the undesirable parasitic effects result from the conductive silicon substrate on which the circuit components, including capacitors, are fabricated. Therefore, the parasitic capacitance component of MOS integrated capacitors can interfere with the RF signals in wireless communication ICs.
Another disadvantage of the MOS capacitor shown in FIGS. 1A and 1B is that there is no isolation provided. Isolation is important for ICs used in wireless communications applications. High isolation, and in particular, high RF isolation, implies that devices can be spaced closer together without adjacent elements interacting with each other, and die size is minimized. The parasitic capacitance to substrate of the integrated MOS capacitor combined with poor isolation can, for example, lead to an amount of local oscillator (LO) signal appearing at the output of the receiver and effectively be transmitted at the antenna. Wireless regulatory authorities limit the amount of spurious signal that can be radiated by the receiver, so limiting the amount of LO radiation is necessary to meet these specifications.
Yet another disadvantage of the MOS capacitor shown in FIGS. 1A and 1B is that it requires a significant amount of silicon area to make a large capacitor, i.e. a capacitor with a high capacitance value.
Thus, there is a need for an apparatus and method that provides an integrated circuit capacitor having a low parasitic capacitance to substrate, high isolation, and a high capacitance per unit area.
The present invention provides an integrated circuit capacitor. The capacitor includes a silicon-on-insulator (SOI) substrate and a doped epitaxial layer of a first conductivity type formed on the SOI substrate. The doped epitaxial layer is used as a first plate of the integrated circuit capacitor. A gate oxide layer is formed on the doped epitaxial layer and is used as a dielectric layer of the integrated circuit capacitor. A polysilicon gate is formed on the gate oxide layer and is used as a second plate of the integrated circuit capacitor.
The present invention also provides an integrated circuit capacitor that includes a substrate and an insulating layer formed on the substrate. A buried layer is formed on the insulating layer, and an epitaxial layer of a first conductivity type formed on the buried layer. A local oxidation silicon layer is formed on the epitaxial layer that surrounds a first selected surface area of the epitaxial layer. A collector is implanted into the epitaxial layer in the first selected surface area of the epitaxial layer. A gate oxide layer is formed on a first portion of the collector, and a polysilicon gate is formed on the gate oxide layer and a first portion of the local oxidation silicon layer.
The present invention also provides a method of forming an integrated circuit capacitor. The method includes: establishing a silicon-on-insulator (SOI) substrate having an insulating layer formed on a substrate; forming a buried layer on the insulating layer; forming an epitaxial layer of a first conductivity type on the buried layer; forming a local oxidation silicon layer on the epitaxial layer that surrounds a first selected surface area of the epitaxial layer; implanting a collector into the epitaxial layer in the first selected surface area of the epitaxial layer; forming a gate oxide layer on the collector; and forming a polysilicon gate on the gate oxide layer and a first portion of the local oxidation silicon layer.